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? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14532b/d mc14532b 8-bit priority encoder the mc14532b is constructed with complementary mos (cmos) enhancement mode devices. the primary function of a priority encoder is to provide a binary address for the active input with the highest priority. eight data inputs (d0 thru d7) and an enable input (e in) are provided. five outputs are available, three are address outputs (q0 thru q2), one group select (gs) and one enable output (e out ). ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14532bcp pdip16 2000/box mc14532bd soic16 48/rail mc14532bdr2 soic16 2500/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc14532bcp awlyyww soic16 d suffix case 751b 1 16 14532b awlyww soeiaj16 f suffix case 966 1 16 mc14532b alyw mc14532bfel soeiaj16 see note 1. mc14532bf soeiaj16 see note 1. mc14532bfr1 soeiaj16 see note 1.
mc14532b http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d2 d3 gs e out v dd q0 d0 d1 d7 d6 d5 d4 v ss q1 q2 e in truth table input output e in d7 d6 d5 d4 d3 d2 d1 d0 gs q2 q1 q0 e out 0 x x x x x x x x 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 x x x x x x x 1 1 1 1 0 1 0 1 x x x x x x 1 1 1 0 0 1 0 0 1 x x x x x 1 1 0 1 0 1 0 0 0 1 x x x x 1 1 0 0 0 1 0 0 0 0 1 x x x 1 0 1 1 0 1 0 0 0 0 0 1 x x 1 0 1 0 0 1 0 0 0 0 0 0 1 x 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 x = don't care
mc14532b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.74 m a/khz) f + i dd i t = (3.65 m a/khz) f + i dd i t = (5.73 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.005.
mc14532b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (8.) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time e e in to e out t plh , t phl = (1.7 ns/pf) c l + 120 ns t plh , t phl = (0.66 ns/pf) c l + 77 ns t plh , t phl = (0.5 ns/pf) c l + 55 ns t plh , t phl 5.0 10 15 e e e 205 110 80 410 220 160 ns propagation delay time e e in to gs t plh , t phl = (1.7 ns/pf) c l + 90 ns t plh , t phl = (0.66 ns/pf) c l 57 ns t plh , t phl = (0.5 ns/pf) c l + 40 ns t plh , t phl 5.0 10 15 e e e 175 90 65 350 180 130 ns propagation delay time e e in to q n t plh , t phl = (1.7 ns/pf) c l + 195 ns t plh , t phl = (0.66 ns/pf) c l + 107 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns t phl , t plh 5.0 10 15 e e e 280 140 100 560 280 200 ns propagation delay time e d n to q n t plh , t phl = (1.7 ns/pf) c l + 265 ns t plh , t phl = (0.66 ns/pf) c l + 137 ns t plh , t phl = (0.5 ns/pf) c l + 85 ns t plh , t phl 5.0 10 15 e e e 300 170 110 600 340 220 ns propagation delay time e d n to gs t plh , t phl = (1.7 ns/pf) c l + 195 ns t plh , t phl = (0.66 ns/pf) c l + 107 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns t plh , t phl 5.0 10 15 e e e 280 140 100 560 280 200 ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. output under v gs = v dd v ds = v out sink current v gs = v dd v ds = v out v dd source current under test d0 thru d7 e in d0 thru d6 d7 e in e out x 0 0 0 1 e ou t q0 x x 0 0 0 0 0 1 1 1 q0 q1 q2 x x x 0 0 0 0 0 0 1 1 1 1 1 1 q2 gs x x 0 0 0 0 1 1 1 1 gs x 0 0 1 1 figure 1. typical sink and source current characteristics figure 2. typical power dissipation test circuit switch matrix external power supply i d e in d0 d1 d2 d3 d4 d5 d6 d7 gs q2 q1 q0 e out v out pulse generator (f o ) e in d0 d1 d2 d3 d4 d5 d6 d7 v ss v dd i d c l c l c l c l c l gs q2 q1 q0 e out 0.01 m f 500 m f
mc14532b http://onsemi.com 5 figure 3. ac test circuit and waveforms programmable pulse generator e in d0 d1 d2 d3 d4 d5 d6 d7 gs q2 q1 q0 e out v dd v ss c l c l c l c l c l note: input rise and fall times are 20 ns 50% 50% 50% 50% 50% 50% 50% 50% 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 50% 10% t phl t phl t phl t phl t phl t thl t thl t thl t thl t plh t plh t plh t plh t plh t plh t plh t tlh t tlh t tlh t tlh t tlh t phl t plh t thl 90% 50% 10% t plh t phl t phl t phl d0 d1 d2 d3 d4 d5 d6 d7 e in e out gs q0 q1 q2 10 11 12 13 1 2 3 4 5 15 14 9 7 6 pin no. 50%
mc14532b http://onsemi.com 6 logic diagram (positive logic) logic equations e out = e in d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 10 11 12 13 1 2 3 4 5 d0 d1 d2 d3 d4 d5 d6 d7 e in 9 7 6 14 15 q0 q1 q2 gs e out q0 = e in (d1 d 2 d 4 d 6 + d3 d 4 d 6 + d5 d 6 + d7) q1 = e in (d2 d 4 d 5 + d3 d 4 d 5 + d6 + d7) q2 = e in (d4 + d5 + d6 + d7) gs = e in (d0 + d1 + d2 + d3 + d4 + 05 + d6 + d7)
mc14532b http://onsemi.com 7 figure 4. two mc14532b's cascaded for 4bit output d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 q1 q0 q2 q1 q0 q2 q1 q0 q2 q3 gs 3/4 mc14071b v dd e in e out e in e out e out = 1" with d in = 0" figure 5. digital to analog and analog to digital converter digital to analog conversion the digital eightbit word to be converted is applied to the inputs of the mc14512 with the most significant bit at x7 and the least significant bit at x0. a clock input of up to 2.5 mhz (at v dd = 10 v) is applied to the mc14520b. a compromise between i bias for the mc1710 and d r between n and pchannel outputs gives a value of r of 33 k ohms. in order to filter out the switching frequencies, rc should be about 1.0 ms (if r = 33 k ohms, c 0.03 m f). the analog 3.0 db bandwidth would then be dc to 1.0 khz. analog to digital conversion an analog signal is applied to the analog input of the mc1710. a digital eightbit word known to represent a dig- itized level less than the analog input is applied to the mc14512 as in the d to a conversion. the word is increm- ented at rates sufficient to allow steady state to be reached between incrementations (i.e. 3.0 ms). the output of the mc1710 will change when the digital input represents the first digitized level above the analog input. this word is the digital representation of the analog word. analog output clock input analog input v dd x7 x6 x5 x4 x3 x2 x1 x0 mc14512 a b c mc1710 r c z v dd v ss e in d0 d1 d2 d3 d4 d5 d6 d7 q2 q0 q1 stop word incrementation q2 q4 q3 q1 q2 q4 q3 q1 ce rce r 1/2 mc14520b 1/2 mc14520b digital input/output 8-bit word to be converted
mc14532b http://onsemi.com 8 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc14532b http://onsemi.com 9 package dimensions soic16 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14532b http://onsemi.com 10 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14532b http://onsemi.com 11 notes
mc14532b http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14532b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk

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